Why Participate?
The increasing complexity of digital circuits brings the need for a design methodology that allows a short design cycle, while maintaining architectural flexibility, re-use of IP blocks and easy documentation.
VHDL is a standard worldwide language for the design, documentation and description of electronic systems on the component, board or system level. It supports design verification through simulation and design creation through synthesis.
Simulation and synthesis are however not the only tools used in the design flow of an ASIC. Digital frontend designers nowadays need also knowledge about a whole set of tools like e.g. static timing analysis, test insertion, power analysis and testpattern generation.
This 5-day course 'VHDL language and design flow' is centered on VHDL syntax (through example) while emphasizing good code style and the link to hardware.
During the course the participants will:
- Be introduced to VHDL and the test-bench concepts.
- Learn how to efficiently simulate VHDL models.
- Be introduced to the VHDL synthesizable sub-set.
- Learn that 'what you write is what you get', i.e. that the synthesized netlist is dependent on how the code is written.
- Learn how to tackle issues like: sharing, asynchronous logic, initialization.
- Get some experience with synthesis of the VHDL code into a gate level netlist using clock gating techniques to reduce the power.
- Learn how to insert basic test logic and generate testpatterns.
- Be introduced to performing power analysis, generating testpatterns and running logic equivalence checks.
Program
Introduction (with Modelsim for simulation)
- Complete flow overview: from specification to tested dies
- VHDL background, versions & basics concepts
- Entities, architectures , process, hierarchy
- Labs
VHDL for synthesis (with Synopsys Design Compiler)
- Packages, libraries, types, signals, variables
- Logic and memory inference
- High level optimizations (resource sharing etc..)
- Labs
VHDL testbenches (VHDL 2008) (with Modelsim)
- Functions, procedures, records, file IO
- Self checking / self stopping
- Coverage
- Labs
Introduction to logic synthesis (with Synopsys Design Compiler)
- Logic synthesis design flow basics
- Timing constraints
- Optimisation control
- Datapath synthesis
- Clock gate insertion
- Scan insertion
- Labs
- Tools used during advanced sy
Final steps before transferring the netlist to the layout team
- ATPG (with Synopsys TetraMax)
- Power analysis (with Synopsys Primetime)
- Formal verification (with Cadence Formality)
- Labs
Objectives
The participants will be taught a thorough understanding of the basic concepts of the VHDL language and its simulation behavior. They will be able to write VHDL models and VHDL test-benches to check their model's functionality and timing behavior. After the course, the participants will be able to write synthesizable VHDL descriptions that translate into netlists of which they can foresee the structure. The participants will also get a basic knowledge of the design steps in the ASIC design flow starting from specification up to a verilog netlist ready for layout.
Required prior knowledge
The participants should know the basics of programming in any standard programming language such as C, Pascal or Fortran. The participants must know about elementary digital hardware design, and concepts such as finite state machine and data-path. A background in Hardware Description Languages such as Verilog will give any participant a head start.
Lecturing team
Roeland Vandebriel, Steven Dupont, Jorgo Tsouhlarakis and Fradaric Joseph
Pricing:
4000 EUR for the course, course material and catering during the course.
Special conditions apply for academic Europractice members. Check the Europractice membership list here to see if your institution is listed. Members should register via the Europractice website: http://www.europractice.stfc.ac.uk/training/
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- Special conditions apply for academic Europractice members. Check the Europractice membership list here to see if your institution is listed. Members should register via the Europractice website: http://www.europractice.stfc.ac.uk/training/.
