Opportunities for permanent roles in a range of business sectors

Senior DFT Engineer

DisplayLink has an exciting key opportunity for a Senior DFT Engineer to carry out hands-on DFT design, implementation and debug using Synopsys DFT tools.

You will bring relevant expertise in large silicon systems implemented in leading technology nodes to improve and shape our DFT methodologies.

In this position you will:

Implement and validate ATPG structures, via:

Partitioning for ATPG and hierarchical approaches

ATPG compression and serialization

Scan insertion and design rule fixing

STA constraints, Primetime execution and timing exception flow

Gate level simulation and debug

 

Validate DFT structures, via:

Synopsys SMS Memory BIST and repair

IP BIST, typically for DDR and SERDES interfaces

VHDL / Verilog design of test structures

System Verilog simulation of DFT test cases

Vector generation, translation and re-simulation

 

Understand and improve test yields, address test vector instabilities, via:

Validation of test structures across PVT (Vector bring-up and characterization)

IP test enhancement and validation, especially high-speed digital interfaces

Assist others in production test program development